This invention relates to semiconductors in general and, in particular, to a semiconductor wafer and to semiconductor devices utilizing the same. The invention specifically pertains to field-effect transistors (FETs), Schottky-barrier diodes (SBDs), and high-electron-mobility transistors (HEMTs), among other semiconductor devices.
The metal-semiconductor FET (MESFET) and HEMT have been both known and used extensively which are made from semiconducting nitrides on silicon substrates. Japanese Unexamined Patent Publication No. 2005-158889 is hereby cited as dealing with these kinds of semiconductor devices. One of the problems with such semiconductor devices arose when they were put to use in a “floating” state, that is, with the potential of the silicon substrate left unfixed. The substrate potential of a floating semiconductor device varied with a DC, AC, or high-frequency voltage impressed to the device, making it unreliable in performance.
One known solution to this problem is the back electrode on the back surface, opposite to the surface on which nitride semiconductor layers are grown, of the silicon substrate. The back electrode has its potential fixed by being electrically coupled to a main electrode (anode in the case of an SBD and a source in the case of an FET) on the nitride semiconductor layers. This solution has proved unsatisfactory because the back electrode may invite a drop in the voltage strength of the device.
Let us consider for example an SBD having a back electrode coupled to its anode. Voltage application between anode and cathode of this SBD also results in that between its cathode and back electrode. As a consequence, when the SBD is turned off (reverse biased), a leakage current may flow not only between cathode and anode but also between cathode and back electrode. It is customary in the semiconductor industry to assess the voltage strength of semiconductor devices in terms of current leakage: The greater the current leakage, the lower is the voltage strength assessment. The susceptibility of the back-electroded SBD to greater current leakage has therefore been a bar to the enhancement of its voltage strength.
In SBDs, FETs and other comparable semiconductor devices, a drop in voltage strength has proved to lessen significantly through reduction of current leakage between cathode and back electrode. This objective is attainable by making thicker the nitride semiconductor layers on the silicon substrate.
However, difficulties have been experienced in growing the nitride semiconductor region to a thickness of, say, five micrometers or more on the substrate. The nitride semiconductor region of such thickness has then been easy to crack, and the complete wafer to warp, by reason of a difference in lattice constant or thermal expansion coefficient between the nitride semiconductor region and the substrate. The cracking of wafers is a serious detriment to the manufacturing efficiency of the semiconductor devices. Warping wafers, on the other hand, may become unusable, being incapable, for example, of being correctly mounted to the fabrication machinery. Even if used one way or another, distorted wafers have been very likely to impede the smooth progress of the manufacturing process. Similar difficulties and inconveniences have been encountered not only with nitride semiconductor devices but with those using other III-V compound semiconductors.